#eda
Eda: 24 AI articles covering eda news, analysis, and research
Articles
Semiconductor Engineering Technical Paper Roundup: October 20⭐8
Semiconductor Engineering's October 20 technical paper roundup highlights new industry research across chip design, verification, manufacturing, packaging, test...
Agentic AI Explores Heterogeneous Chip and Interconnect⭐8
Argonne and UIUC researchers use agentic AI to automate exploration of heterogeneous chip and interconnect architectures, advancing AI-driven semiconductor desi...
Blog Review: October 7 — Key Semiconductor and Design Insights⭐8
Semiconductor Engineering's weekly blog review covers chip design, EDA, manufacturing, advanced packaging, AI hardware, security, and automotive trends shaping ...
From Physical Devices to RTL: Tracing Hardware Design at⭐9
Researchers at Infineon and TU Munich are tracing physical chips back to RTL for hardware security, legacy support, and IP verification, tackling silicon imagin...
Moore's Law AI: Applying Agentic AI Across Chip Design⭐9
Agentic AI moves into production across chip design in 2026, automating design space exploration, physical layout, verification, and cross-domain optimization.
EDA's Future Is Evidence-Driven Automation⭐9
Evidence-driven automation is reshaping EDA as chip complexity surges. Explore why 2026 marks the turning point for traceable, measurable, AI-driven design flow...
When AI Agents Cross Chip Design Silos⭐9
AI agents are breaking down chip design silos, bridging architecture, RTL, verification, and physical implementation to resolve cross-domain trade-offs and redu...
Chip Industry Technical Paper Roundup: September 22, 2026⭐9
Curated semiconductor research digest for September 22, 2026, covering chiplets, advanced packaging, AI-driven EDA, GAA scaling, edge AI, and hardware security.
Agentic AI Automates Design-Rule Repair While Preserving Layout⭐9
Purdue researchers unveil DRC-Agent, an agentic AI that automatically repairs IC design-rule violations while preserving layout equivalence, cutting manual DRC ...
Reinforcement Learning Cuts Routing Violations in Dense Chip⭐9
NYU researchers apply reinforcement learning to detailed routing, significantly reducing design rule violations in dense chip layouts at advanced nodes.