From Physical Devices to RTL: Tracing Hardware Design at Infineon and TU Munich

Overview

Researchers at Infineon Technologies and the Technical University of Munich (TU Munich) are advancing methods to trace hardware design from physical devices back to register-transfer level (RTL) representations. This work sits at the intersection of reverse engineering, hardware security, and design verification—areas of growing importance as chip complexity and supply-chain scrutiny intensify in 2026.

Why Trace Hardware Back to RTL?

Recovering RTL from a physical chip is valuable for several reasons:

Security analysis: Detecting hidden or malicious logic (hardware Trojans) that may not appear in documentation.
Legacy support: Understanding undocumented or obsolete devices where original design files are lost.
IP verification: Confirming that fabricated silicon matches the intended design specification.
Trust and provenance: Validating that third-party or outsourced components behave as claimed.

The Challenge

Moving from a physical device to RTL is fundamentally difficult. A fabricated chip has already been synthesized, optimized, and mapped to a specific process technology. Reversing this flow requires:

Imaging and delayering the silicon to extract the physical layout.
Netlist extraction to reconstruct the gate-level structure.
RTL inference to abstract the gate-level netlist back into behavioral hardware description language (HDL).

Each stage introduces ambiguity, and the final RTL is rarely identical to the original—it is a functionally equivalent approximation.

The Infineon and TU Munich Approach

The collaboration combines industrial-scale device access with academic research rigor:

Physical analysis: High-resolution imaging and layer-by-layer deprocessing of target devices.
Automated extraction: Tooling to convert physical structures into gate-level netlists.
RTL reconstruction: Algorithms and heuristics that identify recognizable design patterns and map them to RTL constructs.

2026 Context

As of 2026, several trends make this research especially relevant:

Rising supply-chain security requirements push for independent verification of imported and outsourced chips.
Advanced packaging and chiplets add new layers of complexity, since a single package may contain dies from multiple vendors.
AI-assisted EDA is increasingly used to accelerate both design and reverse-engineering workflows.
Regulatory pressure, including hardware security and provenance mandates in key markets, raises demand for traceability from silicon back to source.

Implications

Successful RTL tracing has broad consequences:

Stronger hardware assurance for critical infrastructure, automotive, and defense applications.
Improved design verification and intellectual-property protection.
New research directions in automated reverse engineering and formal equivalence checking.

Conclusion

The work by Infineon and TU Munich illustrates how physical-device analysis, netlist extraction, and RTL reconstruction can be combined into a coherent pipeline. As chips grow more complex and supply chains more distributed, tracing hardware from physical devices back to RTL will remain a cornerstone of hardware security and design trust in 2026 and beyond.

via Semiconductor Engineering

From Physical Devices to RTL: Tracing Hardware Design at