Blog Review: October 21
Semiconductor Engineering's weekly digest of notable technical blog posts across the chip design, manufacturing, and systems ecosystem. Our 2026 review remains focused on the trends shaping silicon today: AI-driven design flows, advanced packaging, and the push toward domain-specific architectures.
Systems & Design
Ed Sperling examines how AI is being folded into EDA tools and verification flows — a trend that has only accelerated into 2026, where agentic AI assistants now handle substantial portions of testbench generation and coverage closure, though engineers still own the critical sign-off decisions. This shift from assisting designers to autonomously generating and refining RTL raises fresh questions about verification completeness and tool trust that the industry is still working through.
Low Power — High Performance
Chips are becoming more heterogeneous, blending multiple processor types, accelerators, and memory technologies onto a single package. In 2026, chiplet-based designs built on standardized interconnect standards like UCIe are increasingly mainstream, and the power/thermal budget challenges of integrating diverse dies — particularly with high-bandwidth memory stacks — remain a central concern for architects balancing performance against energy efficiency.
Manufacturing, Packaging & Materials
Advanced packaging continues to dominate the conversation. The industry's focus on 2.5D and 3D packaging as the path to sustaining performance scaling now includes hybrid bonding in high-volume production and the rise of panel-level packaging as a cost-reduction strategy. As transistor scaling slows, packaging innovation has become inseparable from the process roadmap, with design teams addressing war page, thermal management, and yield challenges alongside fab engineers.
Test, Measurement & Analytics
Test is dealing with far greater complexity as multi-die packages and advanced nodes multiply the number of test insertion points. In 2026, AI-assisted test analytics and adaptive test flows are helping reduce test time and cost, while ensuring that Known Good Die requirements for chiplet assembly can be met economically at scale.
Auto, Security & AI
Automotive and security challenges are colliding as software-defined vehicles require a whole new level of hardware and firmware verification. The increasing use of AI in safety-critical automotive functions — from perception to planning — has brought new focus on functional safety (ISO 26262), reliability, and protection against adversarial attacks. Security is no longer an afterthought; it's a design-time requirement from IP to system level.
This blog review is part of Semiconductor Engineering's ongoing coverage of the systems and design ecosystem. Stay tuned for next week's roundup.