Agentic AI Automates Design-Rule Repair While Preserving Layout Equivalence
Purdue University researchers have developed an agentic AI system that automatically repairs design-rule violations in integrated circuit layouts while maintaining layout equivalence. The work, presented at a leading EDA conference, points to a future where physical verification is no longer a manual bottleneck.
As semiconductor process nodes push below 2nm and advanced packaging becomes mainstream in 2026, design-rule checking (DRC) has grown exponentially more complex. Each new node introduces hundreds of additional rules, and fixing violations often requires weeks of manual iteration. The Purdue team's approach leverages large language models (LLMs) and reinforcement learning to create an autonomous agent that understands layout intent and applies minimal, equivalence-preserving fixes.
How the Agentic AI Works
The system, dubbed DRC-Agent, combines a graph neural network (GNN) that encodes the layout as a hypergraph with an LLM-based reasoning engine. When a DRC violation is detected, the agent:
- Localizes the violation to a minimal set of polygons.
- Proposes a sequence of edit operations (e.g., moving edges, resizing shapes, inserting vias) that resolve the rule.
- Verifies that the edit does not alter the circuit's logical function or electrical characteristics—i.e., preserves layout equivalence.
- Iterates until all violations are cleared or a human is consulted.
- Node complexity: 2nm and 1.4nm nodes have design rules that number in the thousands, with complex interdependencies.
- Talent shortage: Experienced layout engineers are scarce, and manual DRC fixing is time-consuming and error-prone.
- AI maturity: Agentic AI—systems that can plan, reason, and act autonomously—has proven successful in other domains like code generation and robotics. Applying it to EDA is a natural next step.
- Time-to-market pressure: Companies can no longer afford weeks of manual DRC iterations. Automation that preserves equivalence is a competitive advantage.
Crucially, the agent learns from past repair sessions, improving its success rate and reducing the number of edits required. In experiments on a 5nm test chip, DRC-Agent resolved 94% of violations automatically, with an average of 2.3 edits per violation—compared to 5.7 edits for a baseline heuristic.
Preserving Layout Equivalence
Layout equivalence is a strict requirement: any repair must not change the netlist, parasitic parameters, or timing behavior. The Purdue team formalized this as a set of constraints that the agent must satisfy. They use a formal equivalence checker (e.g., a modified version of Calibre LVS) as a reward signal during training, ensuring that the agent never proposes a fix that would alter the design's function. This is a key differentiator from earlier AI-based DRC fixers that often produced electrically different layouts.
2026 Context: Why This Matters Now
In 2026, the semiconductor industry faces a perfect storm:
Purdue's work aligns with a broader industry trend: major EDA vendors are racing to integrate agentic AI into their physical design tools. However, most commercial solutions still rely on rule-based or machine-learning-based fixers that do not guarantee equivalence. Purdue's formal approach could set a new standard.
Limitations and Future Work
The current system handles only geometric DRC violations; it does not yet address antenna rules or density checks. The team is also working on scaling the agent to full-chip layouts, where the search space is vastly larger. They plan to integrate with commercial place-and-route tools and explore multi-agent collaboration for different rule types.
Conclusion
Purdue University's agentic AI for design-rule repair represents a significant step toward fully autonomous physical verification. By preserving layout equivalence, it addresses a critical barrier to adoption. As the industry moves to 2nm and beyond in 2026, such innovations will be essential to keep design productivity on track.
Further reading: The full paper is available in the proceedings of the 2026 Design Automation Conference (DAC).