Carbon-Dot Interface Enables Ultrathin High-κ Dielectrics on 2D Semiconductors
A joint research effort from the University of Illinois Urbana-Champaign (UIUC), the National Energy Technology Laboratory (NETL), Argonne National Laboratory, and Monash University demonstrates a carbon-dot interfacial layer that enables uniform, ultrathin high-κ dielectric growth directly on 2D semiconductors—a long-standing barrier to scaling next-generation transistors.
The Challenge: Integrating High-κ Dielectrics with 2D Materials
Two-dimensional (2D) semiconductors such as transition metal dichalcogenides (TMDs)—including molybdenum disulfide (MoS₂)—offer atomically thin channels with excellent electrostatic control, making them strong candidates for continued transistor scaling beyond silicon. However, integrating these materials with high-κ gate dielectrics has remained difficult.
2D surfaces are chemically inert and lack dangling bonds, which are normally the nucleation sites that allow dielectric films to grow uniformly during atomic layer deposition (ALD). As a result, direct dielectric growth on 2D materials tends to produce discontinuous, non-uniform films, leading to high leakage currents and poor device performance.
The Carbon-Dot Solution
The multi-institution team addressed this problem by introducing carbon dots as an interfacial seeding layer. These nanoscale carbon structures provide a dense, uniform distribution of functional groups that act as nucleation sites for ALD precursors, enabling the conformal growth of high-κ dielectric films—even at thicknesses of just a few nanometers—directly on the 2D surface.
Key advantages of this approach include:
- Uniform nucleation: Carbon dots supply the chemical functionality that pristine 2D surfaces lack, promoting dense, pinhole-free dielectric growth.
- Ultrathin films: High-κ dielectrics can be deposited at thicknesses relevant to aggressively scaled gate stacks, without the defects that typically plague direct deposition.
- Interface quality: The carbon-dot layer mediates the 2D/dielectric interface, helping to suppress leakage and maintain good electrical characteristics.
- Compatibility: The process is compatible with established ALD workflows, easing integration into existing fabrication lines.
Why It Matters in 2026
As the semiconductor industry pushes past the limits of conventional silicon channel scaling—with gate-all-around (GAA) nanosheet devices now in high-volume production and 2D-material channels under active development for sub-2nm nodes—the dielectric interface has become a critical bottleneck. Reliable, ultrathin high-κ dielectrics on 2D semiconductors are essential for realizing low-power, high-performance 2D transistors.
This work directly addresses that bottleneck by providing a scalable route to high-quality gate stacks on 2D channels. It also aligns with broader 2026 momentum in 2D electronics, where research consortia and foundries are racing to mature TMD-based devices for logic, memory, and beyond-CMOS applications.
Institutions Involved
The collaboration brings together complementary expertise:
- University of Illinois Urbana-Champaign (UIUC) — materials science and device engineering
- National Energy Technology Laboratory (NETL) — nanoscale materials and characterization
- Argonne National Laboratory — advanced characterization and synchrotron-based analysis
- Monash University — 2D materials synthesis and interface science
Outlook
The carbon-dot interface approach offers a promising pathway toward manufacturable high-κ dielectrics on 2D semiconductors. If the process can be scaled and integrated into production flows, it could help unlock the next generation of ultrathin, low-power transistors built on 2D channel materials.
Stay tuned to Semiconductor Engineering for continued coverage of 2D material integration and advanced gate stack research.