Single-Crystal High-κ Dielectric Paves the Way for Low-Power 2D CFETs (NUS et al.)
A research collaboration led by the National University of Singapore (NUS) has demonstrated a single-crystal high-κ dielectric that enables low-power complementary field-effect transistors (CFETs) based on two-dimensional (2D) materials—a promising step toward next-generation, energy-efficient electronics.
Background and Motivation
As the semiconductor industry faces the limits of conventional silicon scaling, 2D materials such as transition metal dichalcogenides (TMDs) have emerged as strong candidates for ultrathin channels in future transistors. However, integrating high-quality high-κ dielectrics with 2D materials remains a major challenge. Amorphous dielectrics often suffer from defect-induced interface traps and leakage, degrading device performance and increasing power consumption.
Single-crystal high-κ dielectrics offer a potential solution by providing a defect-free, atomically smooth interface with 2D channels. Yet, growing such dielectrics directly on 2D materials without damaging them has been difficult.
Key Innovation
The NUS-led team developed a method to integrate a single-crystal high-κ dielectric (likely a perovskite-based oxide such as SrTiO₃ or a related material) with 2D semiconductors. The approach enables a clean, van der Waals interface, minimizing interface traps and enabling efficient electrostatic control.
Using this dielectric, the researchers fabricated 2D CFETs—complementary transistors that stack n-type and p-type devices vertically to reduce footprint and improve energy efficiency. The single-crystal dielectric allowed the CFETs to operate at low supply voltages while maintaining steep subthreshold swing and high on/off ratios.
Results and Implications
The demonstrated 2D CFETs exhibited low power consumption, thanks to the high-quality dielectric interface. Key metrics such as subthreshold swing near the thermal limit and reduced leakage current highlight the potential of this approach for future low-power logic applications.
This work addresses a critical bottleneck in 2D electronics: the lack of a scalable, high-quality high-κ dielectric integration scheme. By enabling low-power 2D CFETs, the research moves the field closer to practical monolithic 3D integration and energy-efficient computing.
2026 Context
As of 2026, the semiconductor industry is increasingly focused on 2D materials for sub-2nm technology nodes and beyond. CFETs are widely regarded as a key architecture for extending Moore's Law, with major foundries and research consortia actively developing them. The NUS-led demonstration of a single-crystal high-κ dielectric for 2D CFETs aligns with the industry's push toward low-power, high-performance devices and could accelerate the adoption of 2D materials in future logic technologies.
Conclusion
The integration of single-crystal high-κ dielectrics with 2D semiconductors represents a significant advance in transistor technology. By enabling low-power 2D CFETs, this research—led by NUS and collaborators—offers a promising pathway for next-generation, energy-efficient electronics.