Nanoelectromechanical Switches: A Path to More Efficient Embedded DRAM
Researchers from UC Berkeley, Samsung, and Intel are exploring nanoelectromechanical switches (NEMS) as a promising route to more energy-efficient embedded DRAM (eDRAM). As demand for on-chip memory grows in the AI and edge-computing era, this collaboration highlights a potential shift in how future eDRAM cells could be designed.
Why Embedded DRAM Needs a Rethink
Embedded DRAM integrates DRAM directly onto logic chips, offering higher density than SRAM and lower cost per bit. However, conventional eDRAM relies on continuous refresh cycles to retain data, which consumes significant powerβa growing concern as chips pack more memory closer to compute.
The NEMS Advantage
Nanoelectromechanical switches use physical, mechanical movement at the nanoscale to open and close circuits. Unlike transistor-based memory, NEMS devices can provide near-zero leakage current in the off state, making them attractive for low-power memory applications. By replacing or augmenting conventional access transistors in eDRAM cells, NEMS could reduce refresh overhead and improve energy efficiency.
Collaborative Research
The joint effort between UC Berkeley, Samsung, and Intel reflects a broader industry trend toward exploring beyond-CMOS technologies for memory. While still in the research phase, the work signals that NEMS-based eDRAM could become a viable option as scaling conventional DRAM faces increasing physical and power limits.
Outlook for 2026 and Beyond
As of 2026, the semiconductor industry continues to invest heavily in energy-efficient memory architectures to support AI workloads at the edge and in data centers. NEMS-based eDRAM remains an emerging research direction, but the involvement of major players like Samsung and Intel suggests it is being seriously evaluated for future technology nodes.
Source: Semiconductor Engineering