Characterizing Charge Components in TMD-Based MOS Structures
Overview
Researchers from imec, KU Leuven, and ASM have published work on characterizing the charge components present in metal-oxide-semiconductor (MOS) structures built on transition metal dichalcogenides (TMDs). As TMDs such as MoS2 and WS2 emerge as leading channel candidates for sub-2 nm technology nodes and beyond-silicon logic in 2026, accurate accounting of trapped and fixed charge in the gate stack becomes critical to device performance, threshold-voltage stability, and reliability.
Why Charge Characterization Matters for TMD Devices
In conventional silicon MOS stacks, the origin and behavior of oxide charge is well understood and tightly controlled through mature process integration. TMD-based MOS structures differ in several important ways:
- Van der Waals surfaces: TMDs lack dangling bonds, which changes how the gate dielectric nucleates and how interface states form.
- Thin, high-k gate stacks: Atomic layer deposition (ALD) of high-k dielectrics directly on TMDs often produces non-ideal interfaces, introducing additional trapped charge.
- Transfer and integration effects: Processing steps such as transfer, encapsulation, and annealing can introduce mobile or fixed charge that is not present in the as-grown material.
Because threshold voltage in TMD MOSFETs is highly sensitive to even small charge densities, separating the individual charge components—interface traps, fixed oxide charge, mobile ionic charge, and border traps—is essential for predictive device modeling and for qualifying gate-stack processes.
Charge Components of Interest
The study distinguishes the main contributors to net charge in a TMD MOS capacitor:
- Interface trapped charge (Dit): Energy-dependent states at the TMD/dielectric interface that exchange carriers with the channel.
- Fixed oxide charge (Qf): Immobile charge near the dielectric interface, typically related to process-induced defects.
- Mobile ionic charge (Qm): Contaminants such as alkali ions that drift under bias and cause hysteresis.
- Border/oxide trapped charge (Qot): Carriers trapped within the bulk dielectric, often near the interface, that respond slowly to bias.
- Frequency-dependent C–V: Distinguishing fast interface states from slower border traps by sweeping measurement frequency.
- Temperature-dependent measurements: Extracting activation energies to identify trap mechanisms.
- Bias-stress and hysteresis analysis: Quantifying mobile charge and slow trapping effects through bidirectional sweeps.
- Physical modeling: Correlating extracted charge densities with gate-stack composition and deposition conditions.
- Gate-stack engineering: Selecting dielectric precursors and ALD conditions that minimize interface trap density.
- Threshold-voltage control: Improving Vt stability and reducing variability across the wafer.
- Reliability projections: Understanding how charge redistribution evolves under bias and temperature over device lifetime.
Methodology
The team applies capacitance–voltage (C–V) and conductance-based characterization techniques adapted for TMD-based MOS capacitors. Key methodological considerations include:
Key Findings and Implications
The work highlights that charge in TMD MOS structures is not dominated by a single mechanism; rather, interface traps and fixed charge coexist and must be separated experimentally. This has direct consequences for:
2026 Context
As the industry moves toward 2D-material channels for continued scaling—driven by demands from AI accelerators, edge inference, and low-power logic—TMD MOS characterization has shifted from fundamental research to a manufacturability requirement. In 2026, foundries and equipment vendors are actively integrating TMD channels with high-k/metal gate stacks, and standardizing charge-extraction methodologies is a prerequisite for yield learning and design-technology co-optimization (DTCO).
Conclusion
The imec–KU Leuven–ASM collaboration provides a structured framework for identifying and quantifying the individual charge components in TMD-based MOS structures. By separating interface, fixed, mobile, and border charge, the work supports more accurate device models and more reliable gate-stack process development—an essential step as TMD channels approach commercial deployment.