As hardware security threats grow more sophisticated, pre-silicon verification teams are adopting techniques that go beyond traditional functional testing. Among the most promising approaches is hardware information-flow tracking (IFT), a method that models how sensitive data propagates through a design so that confidentiality and integrity violations can be caught before tape-out. In 2026, with increasingly complex chiplets and AI-driven flows, IFT has become a key component of secure hardware development.
Why Information-Flow Tracking?
Conventional verification focuses on whether a circuit computes the correct output. Information-flow tracking asks a different question: where does secret data go, and can it leak? By assigning security labels to signals and tracking how those labels propagate through logic, IFT can expose:
- Explicit leaks, where sensitive data is written to an observable output.
- Implicit leaks, where a secret influences control flow (for example, branching on a key bit).
- Timing and side-channel effects at the microarchitectural level, when labels interact with speculative or out-of-order structures.
Because these problems are far cheaper to fix before fabrication, IFT is increasingly being integrated into pre-silicon security testing flows rather than treated as a post-silicon audit.
Research Highlights from Princeton, MIT, and EPFL
Leading academic groups have pushed IFT from theoretical models to practical EDA-integrated tools:
- Princeton University has developed gate-level and RTL-level tracking methodologies that annotate nets with security labels and propagate them through the design hierarchy. Their work emphasizes scalability and compatibility with standard synthesis flows.
- MIT researchers have explored formal, proof-based IFT, using model checking and theorem-proving techniques to provide strong guarantees that no unlabeled path can leak information. This complements dynamic or simulation-based approaches.
- EPFL has contributed to compositional and microarchitectural IFT, addressing how labels must be handled across speculative execution, caches, and shared resources in modern processors.
Together, these efforts show a spectrum of solutions, from lightweight, simulation-friendly tagging to rigorous formal verification.
Practical Integration Challenges
Adopting IFT in production flows is not without obstacles:
- Label explosion and scalability – Tracking every signal can be expensive. Research focuses on abstraction and selective tracking to keep runtime manageable.
- Tool interoperability – IFT must connect with existing RTL, netlist, and formal verification tools, which often have incompatible data models.
- Coverage and soundness – Teams must decide when a dynamic IFT run is sufficient versus when a formal proof is required.
- 2026 context – With heterogeneous integration and AI-assisted design exploration, tracking must span multiple chiplets and third-party IP, raising new trust and label-management issues.
Outlook
Pre-silicon information-flow tracking is moving from a niche research topic toward an expected part of secure hardware signoff. As foundries and EDA vendors add IFT-aware features and standards mature, the Princeton, MIT, and EPFL work provides the methodological foundation for building designs that are not only functionally correct but demonstrably trustworthy.
For verification teams, the takeaway is straightforward: treat information flow as a first-class verification concern, and start tracking it early.