M3D 6T SRAM with BEOL Pass-Gates at 2nm
Researchers from Georgia Tech and Synopsys have unveiled a significant advancement in memory technology: a monolithic 3D (M3D) 6-transistor (6T) static random-access memory (SRAM) cell that leverages back-end-of-line (BEOL) pass-gates, fabricated at the 2nm technology node. This work addresses critical challenges in cache density and energy efficiency as the semiconductor industry pushes beyond the 3nm frontier.
The Challenge: SRAM Scaling in the Post-FinFET Era
As logic transistors shrink, conventional SRAM scaling has become increasingly difficult. The physical footprint of 6T SRAM cells—traditionally laid out entirely in the front-end-of-line (FEOL)—limits area scaling and creates routing congestion. Moreover, with the transition from FinFETs to gate-all-around (GAA) nanosheet transistors at 2nm and below, the integration density of peripheral circuits and cache arrays faces new constraints. The industry needs innovative bitcell architectures to maintain the performance-per-area gains that memory hierarchies have historically delivered.
The Innovation: Moving Pass-Gates to the BEOL
A key innovation in this work is the relocation of the pass-gate transistors in a 6T SRAM bitcell to the BEOL, using monolithic 3D integration. In a conventional 6T SRAM, two pass-gates control access to the cross-coupled inverters. By fabricating these pass-gates in the BEOL—primarily enabled by advancements in low-temperature polysilicon or other thin-film transistor (TFT) technologies—the researchers reclaim significant FEOL area. This enables:
- Higher cell density: The FEOL is reserved for the cross-coupled inverters and drive transistors, reducing area per bit by up to 30% compared to planar or FinFET-based 6T designs.
- Reduced bitline capacitance: BEOL pass-gates can be placed closer to bitlines and wordlines, shortening interconnect paths and lowering parasitic capacitance.
- Improved energy efficiency: Lower capacitance directly translates to reduced dynamic power, especially in high-frequency read/write operations.
Monolithic 3D Integration: A Manufacturing-Ready Approach
Georgia Tech’s M3D approach uses sequential layer transfer and low-temperature processing (below 400°C) to build the BEOL transistors over the FEOL layer, ensuring compatibility with existing BEOL metallization and dielectric stacks. In collaboration with Synopsys, the team performed comprehensive design-technology co-optimization (DTCO) using industry-grade simulation tools, including:
- 3D physical design and parasitic extraction to assess interconnect delays.
- Transistor-level simulation with calibrated models for BEOL TFTs, including variability analysis.
- Full memory macro-level evaluation encompassing read/write margins, SNM (static noise margin), and temperature stability.
The results demonstrate robust operational margins with a 15–20% improvement in read/write energy-delay product (EDP) over conventional 6T SRAM at similar density, along with a reduced bitline delay by up to 25%.
Implications for 2nm and Beyond
This research arrives at a pivotal moment. By 2026, major foundries are transitioning to 2nm-class GAA processes, where SRAM area is expected to be a limiting factor for SoC scaling. The BEOL pass-gate approach offers a path forward that avoids the complexity of fully heterogeneous integration found in some complementary FET (CFET) proposals. Instead, it leverages mature, cost-effective BEOL processing, making it a pragmatic solution for:
- L3 cache and large on-chip SRAM arrays in high-performance computing (HPC) and AI accelerators.
- Ultra-low-power SRAM for edge AI devices where leakage and dynamic power are critical.
- Future CFET and stacked FET architectures, where the FEOL layer may become even more constrained.
Looking Ahead
The collaboration between Georgia Tech and Synopsys provides a blueprint for industry adoption, demonstrating that M3D SRAM with BEOL pass-gates can be validated within a standard design flow, using tools that are already available. As 2nm ramp continues, we can expect further refinements—such as the use of oxide-semiconductor (e.g., IGZO) BEOL pass-gates to reduce leakage further—and broader adoption of M3D techniques in memory and logic integration. This work is a significant milestone in the journey toward truly three-dimensional integrated circuits, where the memory hierarchy itself is reimagined at the node level.