Voltage droop—the transient dip in supply voltage caused by sudden current demand—remains a critical challenge in advanced chiplet-based systems. In 2.5D processing-in-memory (PIM) architectures, where logic chiplets and memory dies are integrated on a silicon interposer, droop can severely degrade performance, trigger timing violations, and even cause functional failures. As we move deeper into 2026, with PIM gaining traction in AI and high-performance computing, addressing droop has become a top priority for packaging and power-integrity engineers.
Researchers from Washington State University and the University of Wisconsin-Madison have proposed a systematic approach to controlling voltage droop in 2.5D PIM chiplet systems. Their work focuses on optimizing the power delivery network (PDN) at both the chiplet and package levels, leveraging a combination of on-chip decoupling capacitors, interposer-level power routing, and dynamic voltage regulation techniques.
The Voltage Droop Problem in 2.5D PIM
In 2.5D integration, logic chiplets and memory stacks share a common silicon interposer. The interposer provides high-density interconnect but also introduces path inductance that can worsen droop. When memory access patterns cause rapid switching in PIM logic, the resulting current transients can produce droop spikes of 10-20% of the nominal supply voltage, especially under high-frequency operation. This is particularly serious in PIM architectures because memory-intensive workloads—like deep neural network inference—induce large, rapid changes in current draw.
Traditional mitigation methods, such as external VRM (voltage regulator module) placement and board-level bulk capacitors, are often too slow or too far from the load to respond effectively. Moreover, the physical constraints of 2.5D packages limit the addition of large decoupling capacitance directly on the logic dies.
Proposed Solutions
The research team proposes a multi-layered mitigation strategy:
- Interposer-Level Power Routing Optimization: By re-designing the power grids embedded in the silicon interposer, the researchers reduced effective loop inductance by up to 30%, decreasing droop amplitude under identical load conditions.
- Hierarchical Decoupling Capacitor Placement: Instead of relying on a single large on-chip capacitor, they advocate for a distributed network of small, high-density capacitors placed both on the interposer and within the memory arrays. This provides faster response times and better noise suppression across a wider frequency spectrum.
- Dynamic Voltage and Frequency Scaling (DVFS) with Predictive Control: Using machine learning-based prediction of workload-induced current transients, the system adjusts supply voltage and clock frequency preemptively, reducing the rate of current change (di/dt) and thus droop severity.
Experimental Results
Simulations on a prototype 2.5D PIM system (comprising a 5nm logic chiplet and 3D-stacked memory dies) demonstrated that the combined approach cuts peak droop by 58% compared to a baseline device, while maintaining power efficiency. The proposed design also improved timing margin by 22%, allowing higher operating frequencies or reduced supply voltage for the same performance target—an important benefit for power-constrained AI accelerators.
The research underscores the importance of co-design between architecture, packaging, and power delivery. As chiplet-based PIM moves toward mainstream adoption in 2026 and beyond, such integrated approaches will be vital for ensuring reliable, high-performance operation in next-generation systems.