#semiconductor design
Semiconductor Design: 12 AI articles covering semiconductor design news, analysis, and research
Articles
Foundation IP for the AI Era: Why Execution Saves You MillionsNEWβ9
Discover why superior foundation IP execution is critical for HPC and edge AI SoCsβreducing integration risks, avoiding costly respins, and saving millions.
Designing Physical AI Systems Under Real-World Constraintsβ9
Physical AI systems must work reliably under real-world power, latency, and safety constraints. Learn how to design hardware and models together for deployment.
EDA's Future Is Evidence-Driven Automationβ9
Evidence-driven automation is reshaping EDA as chip complexity surges. Explore why 2026 marks the turning point for traceable, measurable, AI-driven design flow...
Building a Connected, Contextual Data Backbone for AI-Drivenβ9
AI-driven semiconductor design requires a connected, contextual data backbone to unify siloed design, verification, and manufacturing data for smarter chip work...
Can AI Agents Design Better Chips at Higher Abstraction withβ10
UCLA research explores whether AI agents using High-Level Synthesis can design better chips at higher abstraction, outperforming traditional RTL-based approache...
Agentic AI Automates Design-Rule Repair While Preserving Layoutβ9
Purdue researchers unveil DRC-Agent, an agentic AI that automatically repairs IC design-rule violations while preserving layout equivalence, cutting manual DRC ...
EBook β Accelerate Silicon Design for Physical AI (Part 1)β9
Discover how silicon design is evolving for Physical AI in 2026βreal-time processing, energy efficiency, and safety innovations.
Trust, But Verify: Ensuring Reliability in AI-Drivenβ9
Discover how AI transforms chip design and verification in 2026, and why robust strategies like formal and cloud-based testing ensure reliability.
Cycle-Level Simulator for Distributed GPUs in AI Workloads (Purdue)β9
Cycle-level distributed GPU simulator for AI workloads, modeling compute, memory, interconnects, and power for 2026 data center design.
GPU-Accelerated Differentiable Framework Resolves Speed-Accuracyβ8
A GPU-accelerated differentiable framework from Duke and Synopsys speeds up switching power analysis without sacrificing accuracy, resolving the speed-accuracy ...