#chiplet
Chiplet: 6 AI articles covering chiplet news, analysis, and research
Articles
Finding Critical Defects Before They Become Costly Failures:⭐10
Hybrid bonding and advanced packaging process control: detect critical defects like voids, misalignment, and contamination before they cause costly multi-die fa...
Make Your Interface Work For Your AI SoC—A 10-Step Program: IP⭐9
As AI SoCs hit bandwidth limits, our 10-step program guides architects through HBM4, UCIe 2.0, NoC, and chiplet IP choices to build an optimal interface.
Chiplet Co-Design Framework Cuts Energy and Design Costs for AI⭐9
A University of Michigan chiplet co-design framework reduces energy use and design costs for AI accelerators via machine learning and energy-aware partitioning.
Unified Chiplet Network Scales Neuromorphic Computing Systems⭐9
Heidelberg researchers propose a unified chiplet interconnect architecture to scale neuromorphic spiking neural networks beyond single-chip limits, enabling ene...
Why SoC Interconnects Have Outgrown the Bus⭐10
SoC interconnects have outgrown the shared bus: exploding master counts and AI accelerators demand bandwidth that traditional bus architectures can no longer de...
Open-Source Benchmark Suite for 2.5D/3D Heterogeneous⭐7
UCLA releases open-source benchmark suite for 2.5D/3D heterogeneous integration physical design, enabling standardized testing of placement, routing, and therma...