#ai accelerators
Ai Accelerators: 10 AI articles covering ai accelerators news, analysis, and research
Articles
Profiling TorchNeuron (Part 1): System-Level Profiling on AWS Trainiumβ8
Learn system-level profiling techniques for TorchNeuron on AWS Trainium: key metrics, tooling, environment setup, and best practices for optimizing deep learnin...
Scaling Data Movement for Physical AI: The Interconnect andβ9
Physical AI faces a data movement bottleneck: discover how interconnect and memory bandwidth constraints shape the scaling of robots, autonomous vehicles, and e...
TorchNeuron: Running Hugging Face Models on AWS Trainium Isβ9
TorchNeuron simplifies running Hugging Face Transformers models on AWS Trainium, cutting boilerplate so teams can train and serve models with familiar PyTorch w...
Breaking the Memory Bottleneck in AI and HPC SoCsβ10
Discover how AI and HPC SoCs are overcoming the memory bottleneck with HBM4, advanced DRAM, and new architectures for higher bandwidth and efficiency.
On-Chip Monitors Detect Bit-Flip Attacks in AI Acceleratorsβ9
Researchers develop lightweight on-chip monitors that detect bit-flip attacks in AI accelerators with under 5% area and power overhead, enabling real-time anoma...
HBF for High-Throughput LLM Serving: UC Berkeley and FuriosaAI'sβ9
UC Berkeley and FuriosaAI use Hybrid Bonding Foundation (HBF) tech to boost LLM inference throughput with higher memory bandwidth and lower latency.
The Hidden Challenges of Edge AI Designβ9
Edge AI design hides tough challenges in power, memory, and model compression. Learn the trade-offs engineers must solve for real-time, low-latency inference.
Make Your Interface Work For Your AI SoCβA 10-Step Program: IPβ9
As AI SoCs hit bandwidth limits, our 10-step program guides architects through HBM4, UCIe 2.0, NoC, and chiplet IP choices to build an optimal interface.
Heterogeneous Memory Chiplets Accelerate Multi-Request LLMβ9
NUS researchers propose heterogeneous memory chiplets that combine high-bandwidth, high-capacity, and near-memory compute to accelerate multi-request LLM infere...
Validation Gets Tested at 1kW: Power Demands Reshape Siliconβ9
As AI chips push past 1kW TDP, silicon validation teams face new power delivery, thermal, and signal integrity challenges. Here's how validation labs are adapti...