Chip Industry Technical Paper Roundup: Sep. 1
Wafer-scale optical interconnects for LLM training; Rowhammer-based inference attacks; 3D-IC test cases; liquid cooling for 2.5D/3D packages; wafer-scale 2D semi growth; DL-based parameter extraction for 2D transistors; and chip-placement optimization.
New technical papers recently added to Semiconductor Engineering’s library:
| Technical Paper | Research Organizations |
|---|---|
| Thermal Tuning Overhead in Wafer-Scale Optical Interconnects for LLM MoE Training: A Cross-Layer Analysis and Ferroelectric-Based Mitigation | Georgia Tech |
| ROBBIN: Rowhammer-Based Backdoor Injection during Inference | Northeastern University |
| An Open-Source Benchmark Suite of 3D-IC Testcases | UCLA |
| Generative Design of Liquid-Cooling Channels for Thermal Management of 2.5D and 3D Integrated Advanced Packaging | University of Michigan-Dearborn |
| Homo-metal-element Mediated Surface Modification of Sapphire for Robust Epitaxy of Wafer-Scale Single-Crystalline 2D Semiconductors | Peking University, ShanghaiTech University, Chinese Academy of Sciences et al. |
| Deep Learning to Automate Parameter Extraction and Model Fitting of Two-Dimensional Transistors | Stanford University, SLAC |
| PPAPlace: Differentiable Cross-Stage Objectives for Chip Placement Optimization | University of Alberta |
Find more semiconductor research papers here.
Tags: Chinese Academy of Sciences Georgia Institute of Technology Northeastern University Peking University semiconductor research ShanghaiTech University SLAC National Accelerator Laboratory Stanford University UCLA University of Alberta University of California Los Angeles University of Michigan-Dearborn
Linda Christensen
(all posts)Linda Christensen is vice president of operations and a contributing writer at Semiconductor Engineering.
Technical Papers
- Workload-Driven HBF Substrate For Capacity-Scalable LLM Inference (Huawei, ETH Zurich, HUST) August 31, 2026 by Technical Paper Link
- Hybrid HBM-HBF Architecture in LLM Inference (University of Oxford) August 30, 2026 by Technical Paper Link
- M3D 6T SRAM With BEOL Pass-Gates at 2nm (Georgia Tech, Synopsys) August 30, 2026 by Technical Paper Link
- Intrinsic Polarization Superjunctions Boost GaN-On-Silicon Power Devices (EPFL) August 30, 2026 by Technical Paper Link
- Cycle-Level Simulator for Distributed GPUs For AI Workloads (Purdue) August 30, 2026 by Technical Paper Link
Related Articles
Self-Driving Cars Have An Aging Problem
AI workloads are pushing automotive sensors harder, forcing engineers to rethink how long safety-critical systems can be trusted.
Reducing variation in manufacturing, monitoring behavior over time, and targeting specific workloads can have a big impact on power, performance, and area/cost.
by Ed Sperling
AI Agent Orchestration For ASIC Autonomy
How to achieve a 10X productivity improvement using AI agents.
by Ed Sperling
Flash Getting Stacked High-Bandwidth Version
Inspired by HBM, HBF could improve AI efficiency in 3D flash memory.
by Bryon Moyer
HBM Shifts Testing Left To Preserve AI Chip Yield
Testing sooner and more often can improve quality and reduce scrap, but it's also more costly.
by Anne Meixner
S. Korea goes All In on AI; new Dresden power fab; Intel expansion; GM secures memory supply; AI power management funding; mature-node foundry capacity; 300mm fab equipment; McKinsey's map of strategic IC supply; security threats; AI burnout.
by The SE Staff
Onsemi to buy Synaptics; IBM's 7Å chip w/40% more SRAM area; 1nm MoS2 nanotubes; AI pressure points; memory updates; $250M CHIPS Act award; trade secret theft; new advanced packaging site; MEMS capacity; humanoids; earnings.
by The SE Staff
Sponsors
Newsletter Signup
Popular Tags
title">Recent Comments
- Ron Lavallee on From Spec To Formal Properties
- delli on Chip Security Moves From Checkbox Compliance To Continuous Defense
- mark holdaway on From Spec To Formal Properties
- Viska Clanella Nugroho on All AI Data Center Interconnects Will Be Optical Within 5 Years
- Tom Katsioulas on AI: Friend And Foe For Chip Security
- Alex @ APIVALE on Chip Industry Week In Review
- Matt bailey on AI Is Rewriting The IP Playbook
- Matt bailey on AI Models Transform Defect Inspection And Review, But Can Fail To Scale
- Alexis R. Ware on Neural Network Model Quantization On Mobile
- Zack63 on Change Is Tough
- Yağız Boz on EDA/SIP Revenue Up 12.7%; APAC Roars Back
- Murugavel Ganesan on Executive Outlook: Agentic AI’s Impact On Chip Design
- F. Chen on Mask Economics Shape High-NA EUV Adoption
- B.S. Deepaksubramanyan on Designing Chips That Can Explain Themselves
- Brian Bailey on Disturbance In Verification
- David Murray on Disturbance In Verification
- Ramesh Narayanaswamy on Disturbance In Verification
- Cliff Greenberg on Research Bits: Jun. 2
- Peter Ateshian on Detect, Diagnose, And Debug Using Sensors And Functional Monitoring
- Dr. Dev Gupta on Chip Industry Week In Review
- Ed Sperling on The Sub-2nm Paradox
- Jan Hoppe on The Sub-2nm Paradox
- Jan Hoppe on Toward Agentic Verification
- Riko R on With Chiplets, What Role Does Economics Play?
- C Lytle on Flash Getting Stacked High-Bandwidth Version
- Saket Goyal on HBM Shifts Testing Left To Preserve AI Chip Yield
- Debamitro Chakraborti on Creating Agentic EDA Methodologies
- Wim Bakker on Batteries Charge To The Edge
- Ron Richter on TSV Complexity Leads To Manufacturing Bottleneck
- François on The Petabyte Problem: How AI Is Finally Making Semiconductor Manufacturing Data Actionable
- Anonymous on The One Bit Problem That Can Break a System
- JC Bouzigues - IROC Technologies on The One Bit Problem That Can Break a System
- Tom Fitzpatrick on All Software Is Hardware-Dependent
- Anonymous on Memory Wall Gets Higher
- Gregory Haley on Detecting Chemical Variability At Advanced Nodes
- Matt Groves on A Framework That Generates Chip Layouts Directly From Natural Language Specifications (U. of Bristol, RAL)
- AICHIPS on How AI Will Impact Chip Design And Designers
- Martijn Fransen on Detecting Chemical Variability At Advanced Nodes
- Narek on Digital Twins: The Cloud’s The Limit
- Freelancer on Chip Industry Talent Shortage Drives Academic Partnerships
- Chris Riches on Backside Power Delivery Creates Fab Tool, Thermal Dissipation Barriers
- Jon on Robust Dynamic Voltage Droop Mitigation And Power Management
- Ashfaq on Minimum Energy Per Query
- Robert Boissy on Can A Computer Science Student Be Taught To Design Hardware?
- Hank Walker on Can A Computer Science Student Be Taught To Design Hardware?
- fieke khan on Bump Co-Planarity And Inconsistencies Cause Yield, Reliability Issues
- Rajiv on Chip Industry Week in Review
- Guy van der Walt - Thermco on Chiplets And 3D-ICs Add New Electrical And Mechanical Challenges
- Stephen W on Chiplet Fundamentals For Engineers: eBook
- ShrdMem256 on The Verification Conundrum
- Brendan McGuire on Wafer Probe Struggles To Adapt To Multi-Die Assemblies
- NobodyTestedThis on The Verification Conundrum
- Fiber Techs San Francisco on Agentic AI In Chip Manufacturing
- SF Fiber Techs on Oxides Bring Low Leakage Transistors To Leading-Edge Memories
- humic on Addressing Critical Tradeoffs In NPU Design
- Dr. Dev Gupta on Liquid Cooling Gains Traction In Data Centers
- Mikko Utriainen, Chipmetrics on Metrology Digs Deep To Produce Next-Generation 3D NAND
- Raymond Doerr on Wafer Bonding Mechanisms Using SiCN Films For Hybrid Bonding Applications In 3D Integration
- Hoyong Lee on Chiplets Vs. Soft IP: Different In Almost Every Way
- Nano Banana AI on Blog Review: Dec. 17
- JS Paek on Thermal Management In 3D-IC: Modeling Hotspots, Materials, & Cooling Strategies
- Larry K on Chiplets Vs. Soft IP: Different In Almost Every Way
- Seceon.Inc on Resilient And Optimized GenAI Systems
- Linda Christensen on AI With Open And Scaled Data Sharing in IC Manufacturing (NIST)
- komputer on AI With Open And Scaled Data Sharing in IC Manufacturing (NIST)
- Sree on The Thermal Trap: How Dielectrics Limit Device Performance
- David Muncier on China GenAI: Who Will Fill The Vacuum?
- acp on Is There Still a Future for Hard Disk Drives?
- Carlos Borer on Legacy Process Nodes Going Strong
- Raj Sodhi on AI Meets Device Modeling: Transforming Compact Modeling With Machine Learning
- Jaynarayan Tudu on Semiconductor Test Faces Technology Shifts In The AI Era
- Mihai Buta on Why In-Memory Computation Is So Important For Edge AI
- Silver Luis on The Competitive Advantage Of SRAM PUF Technology
- Gretchen Patti on Advanced Packaging: A Key Technology For The Next Generation Of Electronics
- Ev roach on AI Bubble Or Boom?
- Kathleen Murphy-Weber on Chip Industry Week in Review
- Raz on Multi-Die Verification
- Paul C on Scaling Memory With Molybdenum
- JWS on Scaling Memory With Molybdenum
- Klein miller on Electrifying Everything: Power Moves Toward ICs
- Team at Rise Design Automation on What Does Semiconductor Disruption Look Like?
- masa mizuno on Physics Limits Interposer Line Lengths
- Lou Covey on What Does Semiconductor Disruption Look Like?
- Ricardo Shiroma on Complex Mix Of Processors At The Edge
- Cor on Glass Substrates Gain Momentum
- Daya Young on New Antennas And Advanced ICs Needed For 6G
- Subramanian Srikanteswara Iyer on Manufacturing At The Limits
- Doug La Tulipe on Coloring Optical Signals For More Bandwidth In Data Centers
- WH on The Hidden Cost Of Contact Resistance
- Raymond Doerr on Metrology Under Pressure: Detecting Defects in Fine-Pitch Hybrid Bonding
- Raymond Doerr on Manufacturing At The Limits
- Mallikarjun on The Evolution of DRAM
- Klein Miller on Democratizing Design: How The CHIPS Act Is Reshaping EDA And Semiconductor Innovation
- Klein Miller on Lessons From 30 Years In The Trenches On The Future Of Semiconductor Manufacturing
- Jonathan Kolber on Preparing For The Quantum Computing Age
- Pramod Gupta on Challenges In Stacking HBM
- Madeline Lueilwitz on Reconfigurable Single-Walled CNT FeFET (Univ. of Pennsylvania, Yonsei et al.)
- Anne Meixner on Need For KGD Drives Singulated Die Screening
- Capt kirk on Designing A Better Clock Network
- Alex Martin on AI Effort And Money Misplaced
- Hamilton Carter on AI Effort And Money Misplaced
- Ilmu Komunikasi on Reconfigurable Single-Walled CNT FeFET (Univ. of Pennsylvania, Yonsei et al.)
- Giovanni Lostumbo on Will New Processor Architectures Raise Energy Efficiency?
- Brendon Berg on ESD Guns, Transients And Testing…Oh My!
- GD on All About Interconnects
- Raimo on Crisis Ahead: Power Consumption In AI Data Centers
- Fred Chen on Laser-Focused Results: Improving EUV Line Edge Roughness With Ion Beam Etching
- Fred Chen on Many Options For EUV Photoresists, No Clear Winner
- Amba Prasad on Advanced Packaging Fundamentals for Semiconductor Engineers: eBook
- Shakir Ullah on The Race To Replace Silicon
- Hwaiyu Geng, P.E. on Accelerating Semiconductor Process Development Using Virtual Design Of Experiments
- Larry Gus Christiansen on Reducing Risk In The Semiconductor Supply Chain
- Vikas Sharma on RTL Signoff vs. Functional Signoff: What’s The Difference?
- Simone on Crisis Ahead: Power Consumption In AI Data Centers
- Ron Lavallee on Can Today’s Processor Architectures Be More Efficient?
- Rashid on Can Today’s Processor Architectures Be More Efficient?
- Joseph Fjelstad on When Can I Buy A Chiplet?
- Craig Lytle on Can Today’s Processor Architectures Be More Efficient?
- Partha Thirumalai on Cognichip: Using AI To Speed Complex Chip Design
- Gopal raju on Advanced Packaging Fundamentals for Semiconductor Engineers: eBook
Navigation
Close
Privacy Overview
By continuing to use our website, you consent to our Privacy Policy. If you access other websites using the links provided, please be aware they may have their own privacy policies, and we do not accept any responsibility or liability for these policies or for any personal data which may be collected through these sites. Please check these policies before you submit any personal information to these sites.
Necessary cookies are absolutely essential for the website to function properly. This category only includes cookies that ensures basic functionalities and security features of the website. These cookies do not store any personal information.
Any cookies that may not be particularly necessary for the website to function and is used specifically to collect user personal data via analytics, ads, other embedded contents are termed as non-necessary cookies. It is mandatory to procure user consent prior to running these cookies on your website.
Leave a Reply