As artificial intelligence (AI) workloads continue to scale exponentially, the demand for high-bandwidth, low-latency, and energy-efficient data center interconnects has never been greater. In 2026, the industry is witnessing a pivotal shift toward standards-compliant 112G physical layer (PHY) solutions designed specifically for linear optical links. These technologies are emerging as critical enablers for next-generation AI infrastructure, promising to reduce power consumption, lower system cost, and improve signal integrity compared to traditional DSP-based approaches.
The Role of 112G PHY in AI Data Centers
AI training and inference clusters rely on massive parallel data transfers between GPUs, accelerators, and memory pools. Ethernet speeds have advanced to 800G and 1.6T per port, with 112G per-lane signaling becoming the de facto standard for high-density optical modules. A 112G PHY, operating in conjunction with linear optics—where the optical signal is transmitted without digital signal processing (DSP) at the receive end—offers a compelling alternative to conventional PAM4 DSP solutions.
Linear optics, also known as linear-drive or "linear pluggable optics," eliminates the need for power-hungry DSP chips inside the optical module. Instead, the PHY implements equalization and clock recovery on the host side, which simplifies the module design, reduces latency, and cuts power consumption by up to 50% compared to DSP-based modules. For AI clusters that can contain tens of thousands of optical links, these savings translate into significant operational cost reductions and improved sustainability.
Standards Compliance: A Prerequisite for Interoperability
For linear optics to gain widespread adoption, strict adherence to emerging standards is essential. In 2026, several industry bodies and multi-source agreements (MSAs) have defined specifications for 112G linear-drive interfaces, including IEEE 802.3ck (100G per-lane electrical) and the Open Compute Project's (OCP) Linear Pluggable Optics (LPO) specifications. These standards ensure:
- Interoperability between modules, switches, and retimers from different vendors.
- Signal integrity through defined transmitter and receiver specifications, including eye masks and jitter limits.
- Backward compatibility with existing 100G/400G infrastructure, easing migration paths.
A standards-compliant 112G PHY must support advanced features such as feed-forward equalization (FFE), decision feedback equalization (DFE), and continuous time linear equalization (CTLE) to compensate for channel impairments. Moreover, it should provide adaptive equalization algorithms to handle varying fiber lengths and connector losses—common in real-world AI deployments.
Design Challenges and Solutions for Linear Optics
Implementing a linear optic link at 112G per lane presents several technical challenges:
- Channel loss compensation: Aluminum-based and copper-based electrical channels between the host ASIC and the optical module can introduce significant insertion loss. A robust PHY must incorporate high-performance equalizers and perhaps a re-timer on the host side to clean the signal before driving the laser.
- Clock recovery and jitter: Without a DSP in the module, clock and data recovery (CDR) must be performed on the host PHY. The PHY must handle high-frequency jitter and wander, which requires low-noise PLLs and precise timing circuits.
- Power integrity: As link speeds increase, power supply noise can degrade signal quality. Advanced packaging techniques, such as chip-on-wafer-on-substrate (CoWoS), and dedicated power management circuitry help maintain signal stability.
- Testing and validation: Ensuring link reliability across temperature, voltage, and manufacturing extremes is critical. PHY designers must implement built-in self-test (BIST) capabilities and support eye-opening monitors (EOM) to facilitate in-field diagnosing.
Recent advancements in 2026 have introduced PHY IP that integrates these capabilities in a compact, power-efficient manner. These solutions leverage 5nm or more advanced process nodes, enabling higher integration density and lower parasitic capacitance, which is essential for 112G signaling.
Market Adoption and Future Outlook
The market for linear-drive 112G PHY is expanding rapidly. Major cloud service providersand hyperscalers are actively evaluating or deploying LPO-based solutions for AI back-end networks. According to industry analysts, by 2027, linear optics could represent over 30% of the total optical module market for data centers, driven by AI's insatiable bandwidth appetite and the need for energy efficiency.
In parallel, the standards landscape is evolving to support higher lane rates (e.g., 224G) and co-packaged optics. A standards-compliant 112G PHY with a clear upgrade path to 224G will allow infrastructure investments to remain future-proof.
Conclusion
Standards-compliant 112G PHY for linear optics is a cornerstone technology for building efficient, scalable AI infrastructure. By reducing power consumption, lowering costs, and improving performance, it addresses the critical bottlenecks in modern data centers. As the industry moves toward broader LPO adoption, ensuring strict compliance with IEEE and OCP specifications remains paramount. With ongoing innovations in PHY design and optical integration, 2026 marks a turning point—where linear optics transitions from niche experimentation to mainstream implementation, paving the way for the next generation of AI computing.