Deep Learning Automates Parameter Extraction for 2D Transistors
Researchers at Stanford University and SLAC National Accelerator Laboratory have developed a deep learning approach that automates the extraction of key parameters for two-dimensional (2D) transistors. This breakthrough addresses a significant bottleneck in the characterization and modeling of next-generation nanoscale devices, which are critical for continued progress in semiconductor technology through 2026 and beyond.
The Challenge: Manual Parameter Extraction
Traditionally, extracting parameters from 2D transistor measurements—such as carrier mobility, contact resistance, threshold voltage, and subthreshold swing—has been a time-intensive manual process. Engineers and researchers rely on fitting complex physical models to experimental current-voltage (I-V) and capacitance-voltage (C-V) data. This process is not only slow but also prone to human error and variability, especially when dealing with the unique physics of 2D materials like transition metal dichalcogenides (TMDs) or graphene. These materials exhibit non-ideal behaviors—including Schottky barriers, trap states, and contact-dominated transport—that complicate conventional extraction methods.
The Deep Learning Solution
To overcome these challenges, the Stanford-SLAC team trained a deep neural network on synthetic datasets generated from technology computer-aided design (TCAD) simulations. By teaching the network to recognize the mapping between I-V/C-V characteristics and the underlying physical parameters, the model can rapidly infer the same parameters from real experimental data with high accuracy—often in milliseconds, as opposed to hours or days for manual fitting.
The key advantages of this approach include:
- Speed: Near-instant parameter extraction enables high-throughput characterization, essential for wafer-scale fabrication and process control.
- Consistency: Unlike human analysts, the model yields identical results for identical input, reducing variability.
- Robustness: The network handles noisy or incomplete data more gracefully, providing uncertainty estimates alongside predictions.
- Scalability: The same architecture can be adapted to other device types, including finFETs, nanowires, and emerging 2D heterostructures.
Validation and Performance
The researchers validated their model against both simulated and experimentally measured devices. The extracted parameters matched those obtained from manual extraction within a few percent error, across a wide range of bias conditions and material properties. Furthermore, the model demonstrated excellent generalization, successfully predicting parameters for devices it had never encountered during training—a critical requirement for real-world deployment.
Implications for the Semiconductor Industry
As the industry pushes toward the 2 nm node and beyond, 2D materials are increasingly viewed as potential channel materials that could replace silicon in some applications. However, bringing these materials from research labs to high-volume manufacturing requires precise, fast, and automated characterization methods. This deep learning framework directly addresses that need, offering a pathway to:
- Accelerated process development for 2D material growth and device integration.
- Real-time monitoring during fabrication, enabling adaptive process control.
- Enhanced reliability in device modeling for design-technology co-optimization (DTCO).
In 2026, with the rise of AI-driven semiconductor manufacturing, such machine learning techniques are becoming integral to reducing development cycles and improving yield. The Stanford-SLAC work exemplifies the broader trend of incorporating AI into every stage of semiconductor research and production.
Broader Impact and Future Directions
Beyond parameter extraction, the same approach could be extended to solve inverse problems in other areas of electronics, such as extracting material properties from spectroscopy, predicting degradation from stress tests, or optimizing process parameters in real time. The team is already exploring these possibilities, aiming to create a general-purpose toolkit for automated device characterization.
For researchers and engineers, this development marks a significant step toward fully autonomous semiconductor characterization—a future where AI not only analyzes data but also guides the discovery and optimization of new devices.
Conclusion
The Stanford-SLAC deep learning framework represents a convergence of two powerful trends: the rise of 2D materials and the maturation of AI for scientific discovery. By automating a tedious yet critical task, it accelerates the path from research to production, ensuring that the next generation of transistors is not only smaller but also smarter.
This article is based on research published by Stanford University and SLAC National Accelerator Laboratory, with relevance to current semiconductor technology developments in 2026.