A collaborative research team from RIKEN, Keio University, Los Alamos National Laboratory, and Oak Ridge National Laboratory (ORNL) has developed an advanced processing-in-memory (PIM) simulator with expanded support for 11 distinct memory technologies. This development addresses a critical gap in the semiconductor design ecosystem, where the growing interest in PIM architectures has outpaced the availability of flexible, multi-technology simulation tools.
Expanding Simulation Capabilities for PIM Architectures
Processing-in-memory, which integrates computation directly within memory arrays to reduce data movement bottlenecks, requires accurate simulation across varied hardware configurations. Previously, most simulators were optimized for a single memory type, such as DRAM or SRAM, limiting their utility for exploring emerging non-volatile memories (NVMs) like ReRAM, MRAM, and Phase-Change Memory (PCM). The new simulator breaks this constraint by offering unified support for 11 technologies, enabling researchers and engineers to evaluate trade-offs in performance, energy, and area across the full memory spectrum.
Key features of the simulator include:
- Multi-technology support: Model DRAM, SRAM, and a broad range of emerging NVMs within a single framework.
- Configurable PIM operations: Simulate various PIM computation patterns, including bitwise logic, arithmetic, and data-intensive kernels.
- Scalable performance: Run cycle-accurate simulations for both small-scale prototypes and large-scale HPC workloads.
- Energy-aware modeling: Provide detailed power and energy estimates, critical for PIM adoption in edge and data-center environments.
Architectural Considerations and Design Flexibility
The simulator's architecture follows a modular design, allowing users to plug in custom memory technology parameters and PIM execution models. This flexibility is essential for evaluating different data mapping strategies, control logic, and interconnects in PIM systems. By decoupling memory technology specifications from the core simulation engine, the tool supports both existing and next-generation memory roadmaps, including those anticipated in the 2026–2027 timeframe.
The collaboration between RIKEN and Keio (Japan) and Los Alamos and ORNL (USA) reflects a growing trend toward international partnerships in PIM research, particularly for high-performance computing (HPC) applications. The simulator's design aligns with recent advancements in 3D-stacked memory and chiplets, providing a basis for exploring hybrid memory hierarchies in exascale-era systems.
Benchmarks and Validation
To demonstrate the simulator's capability, the team validated it against hardware implementations and established memory models. Benchmarks include: matrix operations, sparse linear algebra, graph analytics, and neural network inference—all common workloads that benefit from PIM. The simulation results closely match measured energy and latency metrics across multiple technologies, underscoring its accuracy for pre-silicon evaluation.
Implications for the Semiconductor Industry
As PIM moves from academic exploration to commercial adoption, simulation tools that cover diverse memory technologies are critical for reducing design risk and accelerating time-to-market. The new simulator supports this transition by enabling:
- Early-stage algorithm–hardware co-design
- Technology selection for specific application domains
- System-level optimization for energy-constrained devices
- Education and research standardization in PIM design
With the ongoing expansion of AI workloads and data-centric computing, processing-in-memory is expected to play a prominent role in the next generation of chips. This simulator provides a timely, open infrastructure to explore that potential.
The team plans to release the simulator as an open-source project, likely in the spring of 2026, inviting the broader research community to extend its capabilities further.