Synopsys’ Greg Sorber finds that the next era of compute will be defined less by raw speed and more by architectural intelligence, the abstraction of hardware complexity, and the co-design of silicon, software, and systems.

Cadence’s Shyam Sharma looks at what’s in the latest DDR PHY Interface 6.0 specification, including re-centering on newer memories, updated command bus signal naming, and reorganized error reporting.

In a podcast, Siemens’ Tova Levy chats with Andras Vass-Varnai about why 3D-IC reliability can no longer be guaranteed simply by following design rules and what it takes to build it in from the start.

Arm’s Koki Mitsunami checks out how to bring local AI inference to the browser, which becomes part of the AI runtime responsible for model loading, execution, data handling, and interaction with device capabilities.

Keysight’s Quentin Kuperman-Le Bihan suggests that as expectations have risen for increasingly high image quality in consumer electronics, understanding how materials and surfaces scatter light is essential for ensuring peak image quality, robust manufacturing tolerances, and reliable device performance.

SEMI’s Clark Tseng shares highlights from the Surface Preparation & Cleaning Conference, including cleaning innovations for hybrid bonding, next-gen logic wet etch challenges, and DRAM manufacturing.

Plus, check out the blogs featured in the latest Systems & Design newsletter:

Baya Systems’ Nandan Nayampally shows how semiconductor policy shifts affect every company in the industry, regardless of size.

Siemens EDA’s Keith Felton and Todd Burkholder detail why chiplet interface route planning, optimization, and predictive analysis are crucial for achieving PPAC goals.

Arteris’ Insaf Meliane shows how automated connectivity and a single source of truth accelerate SoC assembly while improving design quality.

Synopsys’ Frank Schirrmeister explores the emulation and prototyping hardware that’s taking center stage at DAC 2026.

ChipAgents’ Sidharth Kannan digs into the automation of repetitive, time-consuming behavioral model creation while keeping engineers in the loop.

Vinci’s John Bruggeman argues that engineering intelligence cannot remain fragmented across isolated AI models that understand only narrow slices of physical behavior.

Cadence’s Niyati Singh explains how to translate stress and aging data into measurable design signals for determining whether circuits still meet reliability expectations.

Keysight’s Joo-Ann Beh shows how to reduce patient risk and support regulatory readiness by demonstrating how a wireless device performs in the presence of real world interference.